Processor and Accelerator

project 1: 16 bit ISA MIPS Processor

• 2 core processor
  
• 4 shared L1 cache with least recent used(LRU) page replacement policy
  
• SRAM Controller
  
• Memory Controller through AXI4 interface

project 2: Binary Neural Network Accelerator

• High Level Synthesis Prototype with Xilinx Vitis hls
  
• 2D convolution
  
• RTL micro-architecture optimization
  
• automate synthesis scripting to explore best performance