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add CP15 ICIALLU registers#116

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jonathanpallant merged 2 commits intomainfrom
add-iciallu-reg
Feb 14, 2026
Merged

add CP15 ICIALLU registers#116
jonathanpallant merged 2 commits intomainfrom
add-iciallu-reg

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@robamu
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@robamu robamu commented Feb 11, 2026

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@robamu robamu force-pushed the add-iciallu-reg branch 2 times, most recently from 7ba115c to c825d92 Compare February 11, 2026 10:41
@jonathanpallant
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jonathanpallant commented Feb 11, 2026

Which Arm Architecture versions is this operation applicable to?

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robamu commented Feb 11, 2026

It is applicable to Armv7a and Armv7r (see page 1491 ARM), but also to Armv5 (https://developer.arm.com/documentation/ddi0100/i/?lang=en p.805) . not sure about Armv4. I can not find an Armv4 ARM.

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The v5 ARM usually says when each item was added (i.e new in v5 or was carried over from v4T).

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robamu commented Feb 11, 2026

In ARMv6, the type of cache can be determined from the System Coprocessor register 0, and controlled
through registers 1, 7 and 9. In earlier architecture variants, it is IMPLEMENTATION DEFINED which of these
features are present. All registers are privileged access only unless otherwise defined. Unimplemented
registers are UNDEFINED .

I suppose it is up to the user for older architectures to verify whether this instruction makes sense.

I can add that to the docs.

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LGTM. Just needs the change log entry moving.

@jonathanpallant jonathanpallant added this pull request to the merge queue Feb 14, 2026
Merged via the queue into main with commit fa9b5d0 Feb 14, 2026
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@robamu robamu deleted the add-iciallu-reg branch February 14, 2026 16:50
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2 participants