add CP15 ICIALLU registers

[robamu]

No description provided.

[jonathanpallant]

Which Arm Architecture versions is this operation applicable to?

[robamu]

It is applicable to Armv7a and Armv7r (see page 1491 ARM), but also to Armv5 (https://developer.arm.com/documentation/ddi0100/i/?lang=en p.805) . not sure about Armv4. I can not find an Armv4 ARM.

[jonathanpallant]

The v5 ARM usually says when each item was added (i.e new in v5 or was carried over from v4T).

[robamu]

In ARMv6, the type of cache can be determined from the System Coprocessor register 0, and controlled
through registers 1, 7 and 9. In earlier architecture variants, it is IMPLEMENTATION DEFINED which of these
features are present. All registers are privileged access only unless otherwise defined. Unimplemented
registers are UNDEFINED .

I suppose it is up to the user for older architectures to verify whether this instruction makes sense.

I can add that to the docs.

[jonathanpallant]

LGTM. Just needs the change log entry moving.