Tried running on Verilator #3
Draft
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Verilator don't support `highz` strengh, and I suppose `weak` has equivalent ordering compare to the order strengths used?
Verilator don't support program decls inside a module. This may change the timing of things and cause data races? Not sure how much of a program is this.
Verilator does not support `disable <label>` when `disable` ins't in the scope of `<label>`. Fix it by replacing its uses with a explict bit signal, that is checked by the loop to know if it must exit.
Verilator doesn't support unclocked assertions. I suppose I could also have fixed this by make all assertions sequential, like `assert #0`? Not sure, but I don't need the assertions (for now).
Trying to debug it, the problem came from waiting on delays. The problem is that verilator is design to work on a cycle by cyle basis, and this project uses a lots of delays.
Actually, I think removing all delays make the entire thing don't work anymore. Appear to became stuck on DMA or something? Not sure, appears to not even exit quickboot.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Need to make a bunch of changes because Verilator does not support some features of SystemVerilog.
When I got this running, the simulation was about 100x slower than
vvp. Looking at the logs, Verilator appears to be spending a lot of work waiting for delays.Knowing that Verilator was designed to handle purely cycle-based designs, I guess that the extensive use of delays throughout the project was hitting a pathological case. So I removed all delays.
But when I finally got it to run far enough, the simulation was not working. I guess maybe removing all timings broke it, but could very well have other problems.
I am publishing my work here in case anyone else also wanted to pursue this.