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[PW_SID:1045085] crypto: aegis128: Add RISC-V vector SIMD implementation #1361
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base: workflow__riscv__fixes
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Add a RISC-V vector-accelerated implementation of aegis128 by wiring it into the generic SIMD hooks. This implementation supports vlen values of 512, 256, and 128. Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
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Patch 1: "crypto: aegis128: Add RISC-V vector SIMD implementation" |
PR for series 1045085 applied to workflow__riscv__fixes
Name: crypto: aegis128: Add RISC-V vector SIMD implementation
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1045085
Version: 1