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Security-RISC
Security-RISC PublicProof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
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browser-cpu-fingerprinting
browser-cpu-fingerprinting PublicThis repository contains the code for our paper "Browser-based CPU Fingerprinting".
Repositories
- CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet Public
Vivado 2023.2 project built around the CVA6 RISC-V CPU and a software stack including u-boot and embedded linux.
cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet’s past year of commit activity - cva6 Public Forked from openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cispa/cva6’s past year of commit activity - http-conformance Public
Code for our 2024 ACM AsiaCCS Paper "Who's Breaking the Rules? Studying Conformance to the HTTP Specifications and its Security Impact"
cispa/http-conformance’s past year of commit activity - login-security-landscape Public
Code for our 2024 IEEE S&P Paper "To Auth or Not To Auth? A Comparative Analysis of the Pre- and Post-Login Security Landscape"
cispa/login-security-landscape’s past year of commit activity - LLCSliceReversing Public
Artifact for the IEEE S&P 2025 paper: "Rapid Reversing of Non-Linear CPU Cache Slice Functions: Unlocking Physical Address Leakage"
cispa/LLCSliceReversing’s past year of commit activity - Security-RISC Public
Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
cispa/Security-RISC’s past year of commit activity
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