External clk300

AD9H3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v

@@ -4,6 +4,7 @@
 module flash_vpd_wrapper (
     input            clock_afu
    ,input            clock_tlx
+   ,input            clock_board_ref
    ,input            reset_afu_n
    ,inout            FPGA_FLASH_CE2_L       // To/From FLASH of flash_sub_system.v
    ,inout            FPGA_FLASH_DQ4         // To/From FLASH of flash_sub_system.v

AD9H3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv

@@ -4,6 +4,7 @@
 module flash_vpd_wrapper (
     input            clock_afu
    ,input            clock_tlx
+   ,input            clock_board_ref
    ,input            reset_afu_n
    ,inout            FPGA_FLASH_CE2_L       // To/From FLASH of flash_sub_system.v
    ,inout            FPGA_FLASH_DQ4         // To/From FLASH of flash_sub_system.v

AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v

@@ -4,6 +4,7 @@
 module flash_vpd_wrapper (
     input            clock_afu
    ,input            clock_tlx
+   ,input            clock_board_ref
    ,input            reset_afu_n
    ,inout            FPGA_FLASH_CE2_L       // To/From FLASH of flash_sub_system.v
    ,inout            FPGA_FLASH_DQ4         // To/From FLASH of flash_sub_system.v
@@ -45,11 +46,13 @@ module flash_vpd_wrapper (
 //          Flash Subsystem
 //
 //=============================================================================
-  wire spi_clk;  // 100Mhz
-  BUFGCE_DIV #(.BUFGCE_DIVIDE(2)) spi_clk_inst (
-      .O(spi_clk), .CE(1'b1), .CLR(1'b0), .I(clock_afu)
+  wire spi_clk;  
+  // 100Mhz
+  BUFGCE_DIV #(.BUFGCE_DIVIDE(3)) spi_clk_inst (
+      .O(spi_clk), .CE(1'b1), .CLR(1'b0), .I(clock_board_ref)
   );
 
+
   flash_sub_system FLASH
     (
       // -- Outputs

AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv

@@ -4,6 +4,7 @@
 module flash_vpd_wrapper (
     input            clock_afu
    ,input            clock_tlx
+   ,input            clock_board_ref
    ,input            reset_afu_n
    ,inout            FPGA_FLASH_CE2_L       // To/From FLASH of flash_sub_system.v
    ,inout            FPGA_FLASH_DQ4         // To/From FLASH of flash_sub_system.v

AD9V3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v

@@ -4,6 +4,7 @@
 module flash_vpd_wrapper (
     input            clock_afu
    ,input            clock_tlx
+   ,input            clock_board_ref
    ,input            reset_afu_n
    ,inout            FPGA_FLASH_CE2_L       // To/From FLASH of flash_sub_system.v
    ,inout            FPGA_FLASH_DQ4         // To/From FLASH of flash_sub_system.v

AD9V3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv

@@ -4,6 +4,7 @@
 module flash_vpd_wrapper (
     input            clock_afu
    ,input            clock_tlx
+   ,input            clock_board_ref
    ,input            reset_afu_n
    ,inout            FPGA_FLASH_CE2_L       // To/From FLASH of flash_sub_system.v
    ,inout            FPGA_FLASH_DQ4         // To/From FLASH of flash_sub_system.v