From 7c92ea68ce1bc8b0b06dfc5cf74860c5b7d12491 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Mon, 22 Apr 2024 11:07:48 +0200 Subject: [PATCH 01/27] Add zyboz7 FPGA port --- target/fpga/pulpissimo-zyboz7/.gitignore | 22 +++ target/fpga/pulpissimo-zyboz7/Makefile | 41 +++++ target/fpga/pulpissimo-zyboz7/README.md | 94 ++++++++++ .../pulpissimo-zyboz7/constraints/zyboz7.xdc | 135 +++++++++++++++ .../fpga/pulpissimo-zyboz7/fpga-settings.mk | 7 + .../ips/xilinx_clk_mngr/.gitignore | 21 +++ .../ips/xilinx_clk_mngr/Makefile | 32 ++++ .../ips/xilinx_clk_mngr/tcl/run.tcl | 38 +++++ .../ips/xilinx_slow_clk_mngr/.gitignore | 21 +++ .../ips/xilinx_slow_clk_mngr/Makefile | 32 ++++ .../ips/xilinx_slow_clk_mngr/tcl/run.tcl | 34 ++++ .../rtl/cv32e40p_clock_gate_xilinx.sv | 25 +++ .../pulpissimo-zyboz7/rtl/fpga_bootrom.sv | 36 ++++ .../pulpissimo-zyboz7/rtl/fpga_clk_gen.sv | 89 ++++++++++ .../rtl/fpga_slow_clk_gen.sv | 82 +++++++++ .../rtl/pad_functional_xilinx.sv | 48 ++++++ .../rtl/pulp_clock_gating_xilinx.sv | 27 +++ .../pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v | 161 ++++++++++++++++++ target/fpga/pulpissimo-zyboz7/tcl/.gitignore | 6 + target/fpga/pulpissimo-zyboz7/tcl/common.tcl | 32 ++++ .../tcl/download_bitstream.tcl | 10 ++ target/fpga/pulpissimo-zyboz7/tcl/run.tcl | 113 ++++++++++++ 22 files changed, 1106 insertions(+) create mode 100644 target/fpga/pulpissimo-zyboz7/.gitignore create mode 100644 target/fpga/pulpissimo-zyboz7/Makefile create mode 100644 target/fpga/pulpissimo-zyboz7/README.md create mode 100644 target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc create mode 100644 target/fpga/pulpissimo-zyboz7/fpga-settings.mk create mode 100644 target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/.gitignore create mode 100644 target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/Makefile create mode 100644 target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/tcl/run.tcl create mode 100644 target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/.gitignore create mode 100644 target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/Makefile create mode 100644 target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/tcl/run.tcl create mode 100644 target/fpga/pulpissimo-zyboz7/rtl/cv32e40p_clock_gate_xilinx.sv create mode 100644 target/fpga/pulpissimo-zyboz7/rtl/fpga_bootrom.sv create mode 100644 target/fpga/pulpissimo-zyboz7/rtl/fpga_clk_gen.sv create mode 100644 target/fpga/pulpissimo-zyboz7/rtl/fpga_slow_clk_gen.sv create mode 100644 target/fpga/pulpissimo-zyboz7/rtl/pad_functional_xilinx.sv create mode 100644 target/fpga/pulpissimo-zyboz7/rtl/pulp_clock_gating_xilinx.sv create mode 100644 target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v create mode 100644 target/fpga/pulpissimo-zyboz7/tcl/.gitignore create mode 100644 target/fpga/pulpissimo-zyboz7/tcl/common.tcl create mode 100644 target/fpga/pulpissimo-zyboz7/tcl/download_bitstream.tcl create mode 100644 target/fpga/pulpissimo-zyboz7/tcl/run.tcl diff --git a/target/fpga/pulpissimo-zyboz7/.gitignore b/target/fpga/pulpissimo-zyboz7/.gitignore new file mode 100644 index 00000000..58cd8944 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/.gitignore @@ -0,0 +1,22 @@ +#Ignore vivado project files generated by the tcl script +**/.Xil/* +**/reports/* +**/*.cache/* +**/*.hw/* +**/*.ip_user_files/* +**/*.runs/* +**/*.sim/* +**/*.srcs/* +*.edf +*.xpr +*.jou +*.log + +.cxl.* + +*_stub.v +gmon.out + +/pulpissimo-nexys_video/**/pulpissimo.bit + +**/xdc/constraints.xdc diff --git a/target/fpga/pulpissimo-zyboz7/Makefile b/target/fpga/pulpissimo-zyboz7/Makefile new file mode 100644 index 00000000..e3917cad --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/Makefile @@ -0,0 +1,41 @@ +include fpga-settings.mk + +PROJECT:=pulpissimo-$(BOARD) +VIVADO ?= vivado + +.DEFAULT_GOAL:=help + +.PHONY: help all gui ips clean-ips clk clean-clk clean + +#Make sure BENDER environment variable is available for subprocesses in Make +export BENDER + +all: ips ## Generate the bitstream for pulpissimo with vivado in batch mode. The vivado invocation command may be overriden with the env variable VIVADO. + $(VIVADO) -mode batch -source tcl/run.tcl + +gui: ips ## Generates the bitstream for pulpissimo with vivado in GUI mode. The vivado invocation command may be overriden with the env variable VIVADO. + $(VIVADO) -mode gui -source tcl/run.tcl & + +ips: clk ## Synthesizes necessary xilinx IP + +clean-ips: clean-clk ## Clean all IPs + +clk: ## Synthesizes the Xilinx Clocking Manager IPs + $(MAKE) -C ips/xilinx_clk_mngr all + $(MAKE) -C ips/xilinx_slow_clk_mngr all + +clean-clk: ## Removes all Clocking Wizard IP outputs + $(MAKE) -C ips/xilinx_clk_mngr clean + $(MAKE) -C ips/xilinx_slow_clk_mngr clean + +clean: clean-ips ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) + rm -rf ${PROJECT}.*[^'bit'] + rm -rf ${PROJECT}.*[^'bin'] + rm -rf *.log + rm -rf vivado* + +download: ## Download the bitstream into the FPGA + $(VIVADO) -mode batch -source tcl/download_bitstream.tcl -tclargs $(PROJECT).runs/impl_1/xilinx_pulpissimo.bit pulpissimo_$(BOARD).bit + +help: + @grep -E -h '^[a-zA-Z_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}' diff --git a/target/fpga/pulpissimo-zyboz7/README.md b/target/fpga/pulpissimo-zyboz7/README.md new file mode 100644 index 00000000..728bdb2c --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/README.md @@ -0,0 +1,94 @@ +# PULPissimo on the ZyboZ7 +[\[Documentation\]](https://digilent.com/reference/programmable-logic/zybo-z7/start) + +## Bitstream Generation +In the `fpga` folder, run +```Shell +make zyboz7 +``` +which will generate `pulpissimo_zyboz7.bit`. + +## Bitstream Download +To download this bitstream into the FPGA connect the PROG USB header, turn the board on and run +```Shell +make -C pulpissimo-zyboz7 download +``` + +TODO + + +## Default Frequencies + +By default the clock generating IPs are synthesized from the 100 MHz input (IC17 via Y9) to provide the following frequencies to PULPissimo. +The SoC Frequency is fed into all peripherals as `periph_clk_i`. + +| Clock Domain | Frequency | +|----------------|-----------| +| Core Frequency | 20 MHz | +| SoC Frequency | 10 MHz | + + +## Peripherals +If in doubt please review constraint file for current peripheral mapping in `constraints/zedboard.xdc`. + +### Reset Button +The BTNC is connected as reset button. + +### JTAG +Since there is no way of connecting the RISC-V core to the on-board FTDI USB JTAG programmer you have to attach an external device PMOD A to do so. + +| JTAG Signal | PMOD Pin | +|-------------|----------| +| TMS | JA1 | +| TDI | JA2 | +| TDO | JA3 | +| TCK | JA4 | +| GND | JA5 | +| VCC (trgt) | JA6 | + +The directory holding this README contains OpenOCD configuration files for some known-working adapters. +The commands below are to be executed from within the `fpga` directory. + +#### Digilent HS-2 + +The HS-2 uses the same FTDI chip as the ZedBoard's JTAG port. +So to make it work change the serial number in provided +`openocd-zedboard-hs2.cfg` if you want to have it connected simultaneously with ZedBoard. If you have +Vivado running remember to disconnect the target and close HW Manager before attempting to use OpenOCD. +Otherwise there will be an error about target being busy. + +```Shell +$OPENOCD/bin/openocd -f pulpissimo-zedboard/openocd-zedboard-hs2.cfg +``` + +#### Altera USB Blaster + +After connecting the adapter with 6 jumper wires, simply run: + +```Shell +$OPENOCD/bin/openocd -f pulpissimo-zedboard/openocd-zedboard-usbblaster.cfg +``` + +### UART + +There are UART pins connected to the same PMOD as the JTAG signals (PMOD A), which are utilized by the stdio driver of the PULP SDK (e.g., for the hello example). +The following list depicts the signals (from the FPGA's point of view). + +| UART Signal | PMOD Pin | +|-------------|----------| +| RXD | JA7 | +| TXD | JA8 | +| RTS | JA9 | +| CTS | JA10 | +| GND | JA11 | + +### I2C + +Two pairs of I2C signals are available on PMOD B: + +| Signal | PMOD Pin | +|-----------|----------| +| I2C0_SCL | JB1 | +| I2C0_SDA | JB2 | +| I2C1_SCL | JB3 | +| I2C1_SDA | JB4 | diff --git a/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc b/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc new file mode 100644 index 00000000..e18cda6b --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc @@ -0,0 +1,135 @@ +####################################### +# _______ _ _ # +# |__ __(_) (_) # +# | | _ _ __ ___ _ _ __ __ _ # +# | | | | '_ ` _ \| | '_ \ / _` | # +# | | | | | | | | | | | | | (_| | # +# |_| |_|_| |_| |_|_|_| |_|\__, | # +# __/ | # +# |___/ # +####################################### + + +#Create constraint for the clock input of the ZyboZ7 +create_clock -period 8.000 -name ref_clk_i [get_ports ref_clk_i] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ref_clk] + +## JTAG +create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck] +set_input_jitter tck 1.000 +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] + + +# minimize routing delay +set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi] +set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tms] +set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo] + +set_max_delay -to [get_ports pad_jtag_tdo] 20.000 +set_max_delay -from [get_ports pad_jtag_tms] 20.000 +set_max_delay -from [get_ports pad_jtag_tdi] 20.000 + +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 + + +# reset signal +set_false_path -from [get_ports pad_reset] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_n_IBUF] + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1] + +# increase MTBF +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] +set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*] + +# Create asynchronous clock group between slow-clk and SoC clock. Those clocks +# are considered asynchronously and proper synchronization regs are in place +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +# Create asynchronous clock group between Per Clock and SoC clock. Those clocks +# are considered asynchronously and proper synchronization regs are in place +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]] + +# Create asynchronous clock group between JTAG TCK and SoC clock. +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ + -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] + +############################################################# +# _____ ____ _____ _ _ _ # +# |_ _/ __ \ / ____| | | | | (_) # +# | || | | |_____| (___ ___| |_| |_ _ _ __ __ _ ___ # +# | || | | |______\___ \ / _ \ __| __| | '_ \ / _` / __| # +# _| || |__| | ____) | __/ |_| |_| | | | | (_| \__ \ # +# |_____\____/ |_____/ \___|\__|\__|_|_| |_|\__, |___/ # +# __/ | # +# |___/ # +############################################################# + +## Sys clock +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports ref_clk_i] + +## Reset +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports pad_reset] + +## Buttons +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports btn1_i] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports btn2_i] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports btn3_i] + +## PMOD JE +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tms] +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdi] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdo] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tck] +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports pad_uart_rx] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports pad_uart_tx] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports pad_uart_rts] +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports pad_uart_cts] + +## PMOD JB +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_1] +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_2] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_3] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_4] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_7] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_8] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_9] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports pad_pmodb_10] + +## LEDs +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports led0_o] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports led1_o] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports led2_o] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports led3_o] + +## PMOD JC +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_1] +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_2] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_3] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_4] +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_7] +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_8] +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_9] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports pad_pmodc_10] + +## PMOD JD +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports pad_pmodd_1] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports test_clk_o] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports obs1_o] +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports obs2_o] + +## Switches +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports switch0_i] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports switch1_i] +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports switch2_i] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports switch3_i] diff --git a/target/fpga/pulpissimo-zyboz7/fpga-settings.mk b/target/fpga/pulpissimo-zyboz7/fpga-settings.mk new file mode 100644 index 00000000..892e8851 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/fpga-settings.mk @@ -0,0 +1,7 @@ +export BOARD=zyboz7 +export XILINX_PART=xc7z020clg400-1 +export XILINX_BOARD=digilentinc.com:zybo-z7-20:part0:1.1 +export FC_CLK_PERIOD_NS=62.5 +export PER_CLK_PERIOD_NS=100 +export SLOW_CLK_PERIOD_NS=30517 +$(info Setting environment variables for $(BOARD) board) diff --git a/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/.gitignore b/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/.gitignore new file mode 100644 index 00000000..5099fe9c --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/.gitignore @@ -0,0 +1,21 @@ +#Ignore vivado project files generated by the tcl script +**/.Xil/* +**/reports/* +**/*.cache/* +**/*.hw/* +**/*.ip_user_files/* +**/*.runs/* +**/*.sim/* +**/*.srcs/* +*.edf +*.xpr +*.jou +*.log + +.cxl.* + +*ip + +*_stub.v +gmon.out + diff --git a/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/Makefile b/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/Makefile new file mode 100644 index 00000000..08068a69 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/Makefile @@ -0,0 +1,32 @@ +PROJECT:=xilinx_clk_mngr +VIVADO ?= vivado +VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl +MODE=batch + +include ../../fpga-settings.mk + +.DEFAULT_GOAL:=help + +.PHONY: help all gui clean + +all: MODE=batch ## Create and synthesize the IP in batch mode. + +gui: MODE=gui ## Create and synthesize the IP in GUI mode. + +all gui: $(PROJECT).xpr + +$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl + $(MAKE) clean + $(VIVADO) -mode $(MODE) -source tcl/run.tcl + +clean: ## Remove all build products + rm -rf ${PROJECT}.* + rm -rf component.xml + rm -rf vivado*.jou + rm -rf vivado*.log + rm -rf vivado*.str + rm -rf xgui + rm -rf .Xil + +help: ## Shows this help message + @grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}' diff --git a/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/tcl/run.tcl new file mode 100644 index 00000000..3eb741e2 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/ips/xilinx_clk_mngr/tcl/run.tcl @@ -0,0 +1,38 @@ +source ../../tcl/common.tcl + +# detect target clock +if [info exists ::env(FC_CLK_PERIOD_NS)] { + set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS) +} else { + set FC_CLK_PERIOD_NS 10.000 +} +if [info exists ::env(PER_CLK_PERIOD_NS)] { + set PER_CLK_PERIOD_NS $::env(PER_CLK_PERIOD_NS) +} else { + set PER_CLK_PERIOD_NS 20.000 +} + + +set FC_CLK_FREQ_MHZ [expr 1000 / $FC_CLK_PERIOD_NS] +set PER_CLK_FREQ_MHZ [expr 1000 / $PER_CLK_PERIOD_NS] + +set ipName xilinx_clk_mngr + +create_project $ipName . -part $partNumber +set_property board_part $XILINX_BOARD [current_project] + +create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [eval list CONFIG.PRIM_IN_FREQ {125.000} \ + CONFIG.NUM_OUT_CLKS {2} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.RESET_PORT {resetn} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {$FC_CLK_FREQ_MHZ} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {$PER_CLK_FREQ_MHZ} \ + CONFIG.CLKIN1_JITTER_PS {50.0} \ + ] [get_ips $ipName] + +create_ip_run [get_ips $ipName] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/.gitignore b/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/.gitignore new file mode 100644 index 00000000..5099fe9c --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/.gitignore @@ -0,0 +1,21 @@ +#Ignore vivado project files generated by the tcl script +**/.Xil/* +**/reports/* +**/*.cache/* +**/*.hw/* +**/*.ip_user_files/* +**/*.runs/* +**/*.sim/* +**/*.srcs/* +*.edf +*.xpr +*.jou +*.log + +.cxl.* + +*ip + +*_stub.v +gmon.out + diff --git a/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/Makefile b/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/Makefile new file mode 100644 index 00000000..67d6d935 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/Makefile @@ -0,0 +1,32 @@ +PROJECT:=xilinx_slow_clk_mngr +VIVADO ?= vivado +VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl +MODE=batch + +include ../../fpga-settings.mk + +.DEFAULT_GOAL:=help + +.PHONY: help all gui clean + +all: MODE=batch ## Create and synthesize the IP in batch mode. + +gui: MODE=gui ## Create and synthesize the IP in GUI mode. + +all gui: $(PROJECT).xpr + +$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl + $(MAKE) clean + $(VIVADO) -mode $(MODE) -source tcl/run.tcl + +clean: ## Remove all build products + rm -rf ${PROJECT}.* + rm -rf component.xml + rm -rf vivado*.jou + rm -rf vivado*.log + rm -rf vivado*.str + rm -rf xgui + rm -rf .Xil + +help: ## Shows this help message + @grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}' diff --git a/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/tcl/run.tcl new file mode 100644 index 00000000..8d5b9d6b --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/ips/xilinx_slow_clk_mngr/tcl/run.tcl @@ -0,0 +1,34 @@ +source ../../tcl/common.tcl + +# detect target clock +if [info exists ::env(SLOW_CLK_PERIOD_NS)] { + set SLOW_CLK_PERIOD_NS $::env(SLOW_CLK_PERIOD_NS) +} else { + set SLOW_CLK_PERIOD_NS 30517 +} + +# Multiply frequency by 256 as there is a clock divider (by 256) after the +# slow_clk_mngr since the MMCMs do not support clocks slower then 4.69 MHz. +set SLOW_CLK_FREQ_MHZ [expr 1000 * 256 / $SLOW_CLK_PERIOD_NS] + +set ipName xilinx_slow_clk_mngr + +create_project $ipName . -part $partNumber +set_property board_part $XILINX_BOARD [current_project] + +create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [eval list CONFIG.PRIM_IN_FREQ {125.000} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {$SLOW_CLK_FREQ_MHZ} \ + CONFIG.USE_SAFE_CLOCK_STARTUP {true} \ + CONFIG.USE_LOCKED {false} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.CLKIN1_JITTER_PS {50.0} \ + CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ + CONFIG.RESET_PORT {resetn} \ + ] [get_ips $ipName] + + +create_ip_run [get_ips $ipName] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/target/fpga/pulpissimo-zyboz7/rtl/cv32e40p_clock_gate_xilinx.sv b/target/fpga/pulpissimo-zyboz7/rtl/cv32e40p_clock_gate_xilinx.sv new file mode 100644 index 00000000..5e44ef56 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/rtl/cv32e40p_clock_gate_xilinx.sv @@ -0,0 +1,25 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module cv32e40p_clock_gate ( + input logic clk_i, + input logic en_i, + input logic scan_cg_en_i, + output logic clk_o +); + + pulp_clock_gating i_pulp_clock_gating ( + .clk_i, + .en_i, + .test_en_i (scan_cg_en_i), + .clk_o + ); + +endmodule diff --git a/target/fpga/pulpissimo-zyboz7/rtl/fpga_bootrom.sv b/target/fpga/pulpissimo-zyboz7/rtl/fpga_bootrom.sv new file mode 100644 index 00000000..79d78b3f --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/rtl/fpga_bootrom.sv @@ -0,0 +1,36 @@ +//----------------------------------------------------------------------------- +// Title : FPGA Bootrom for PULPissimo +//----------------------------------------------------------------------------- +// File : fpga_bootrom.sv +// Author : Manuel Eggimann +// Created : 29.05.2019 +//----------------------------------------------------------------------------- +// Description : +// Mockup bootrom that keeps returning jal x0,0 to trap the core in an infinite +// loop until the debug module takes over control. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2019 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +module fpga_bootrom + #( + parameter ADDR_WIDTH=32, + parameter DATA_WIDTH=32 + ) + ( + input logic CLK, + input logic CEN, + input logic [ADDR_WIDTH-1:0] A, + output logic [DATA_WIDTH-1:0] Q + ); + assign Q = 32'h0000006f; //jal x0,0 +endmodule : fpga_bootrom diff --git a/target/fpga/pulpissimo-zyboz7/rtl/fpga_clk_gen.sv b/target/fpga/pulpissimo-zyboz7/rtl/fpga_clk_gen.sv new file mode 100644 index 00000000..0a53727c --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/rtl/fpga_clk_gen.sv @@ -0,0 +1,89 @@ +//----------------------------------------------------------------------------- +// Title : FPGA CLK Gen for PULPissimo +// ----------------------------------------------------------------------------- +// File : fpga_clk_gen.sv Author : Manuel Eggimann +// Created : 17.05.2019 +// ----------------------------------------------------------------------------- +// Description : Instantiates Xilinx clocking wizard IP to generate 2 output +// clocks. Currently, the clock is not dynamicly reconfigurable and all +// configuration requests are acknowledged without any effect. +// ----------------------------------------------------------------------------- +// Copyright (C) 2013-2019 ETH Zurich, University of Bologna Copyright and +// related rights are licensed under the Solderpad Hardware License, Version +// 0.51 (the "License"); you may not use this file except in compliance with the +// License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or +// agreed to in writing, software, hardware and materials distributed under this +// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS +// OF ANY KIND, either express or implied. See the License for the specific +// language governing permissions and limitations under the License. +// ----------------------------------------------------------------------------- + + +module fpga_clk_gen ( + input logic ref_clk_i, + input logic rstn_glob_i, + input logic test_mode_i, + input logic shift_enable_i, + output logic soc_clk_o, + output logic per_clk_o, + output logic cluster_clk_o, + output logic soc_cfg_lock_o, + input logic soc_cfg_req_i, + output logic soc_cfg_ack_o, + input logic [1:0] soc_cfg_add_i, + input logic [31:0] soc_cfg_data_i, + output logic [31:0] soc_cfg_r_data_o, + input logic soc_cfg_wrn_i, + output logic per_cfg_lock_o, + input logic per_cfg_req_i, + output logic per_cfg_ack_o, + input logic [1:0] per_cfg_add_i, + input logic [31:0] per_cfg_data_i, + output logic [31:0] per_cfg_r_data_o, + input logic per_cfg_wrn_i, + output logic cluster_cfg_lock_o, + input logic cluster_cfg_req_i, + output logic cluster_cfg_ack_o, + input logic [1:0] cluster_cfg_add_i, + input logic [31:0] cluster_cfg_data_i, + output logic [31:0] cluster_cfg_r_data_o, + input logic cluster_cfg_wrn_i + ); + + logic s_locked; + + xilinx_clk_mngr i_clk_manager + ( + .resetn(rstn_glob_i), + .clk_in1(ref_clk_i), + .clk_out1(soc_clk_o), + .clk_out2(per_clk_o), + .locked(s_locked) + ); + + assign soc_cfg_lock_o = s_locked; + assign per_cfg_lock_o = s_locked; + + // assign soc_cfg_ack_o = 1'b1; //Always acknowledge without doing anything for now + // assign per_cfg_ack_o = 1'b1; + + always_comb begin + soc_cfg_ack_o = 1'b0; + per_cfg_ack_o = 1'b0; + cluster_cfg_ack_o = 1'b0; + if (soc_cfg_req_i) begin + soc_cfg_ack_o = 1'b1; + end + if (per_cfg_req_i) begin + per_cfg_ack_o = 1'b1; + end + if (cluster_cfg_req_i) begin + cluster_cfg_ack_o = 1'b1; + end + end + + assign soc_cfg_r_data_o = (soc_cfg_add_i == 2'b00 ? 32'hbeef0001 : (soc_cfg_add_i == 2'b01 ? 32'hbeef0003 : (soc_cfg_add_i == 2'b00 ? 32'hbeef0005 : 32'hbeef0007))); + assign per_cfg_r_data_o = 32'hdeadda7a; + +endmodule : fpga_clk_gen diff --git a/target/fpga/pulpissimo-zyboz7/rtl/fpga_slow_clk_gen.sv b/target/fpga/pulpissimo-zyboz7/rtl/fpga_slow_clk_gen.sv new file mode 100644 index 00000000..f3db58f4 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/rtl/fpga_slow_clk_gen.sv @@ -0,0 +1,82 @@ +//----------------------------------------------------------------------------- +// Title : FPGA slow clk generator for PULPissimo +//----------------------------------------------------------------------------- +// File : fpga_slow_clk_gen.sv +// Author : Manuel Eggimann +// Created : 20.05.2019 +//----------------------------------------------------------------------------- +// Description : Instantiates Xilinx Clocking Wizard IP to generate the slow_clk +// signal since for certain boards the available clock sources are to fast to +// use directly. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2019 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +module fpga_slow_clk_gen + #( + parameter CLK_DIV_VALUE = 256 //The xilinx_slow_clk_mngr is supposed to + //generate an 8.3886MHz clock. We need to divide it + //by 256 to arrive to a 32.768kHz clock + ) + (input logic ref_clk_i, + input logic rst_ni, + output logic slow_clk_o + ); + + + + localparam COUNTER_WIDTH = $clog2(CLK_DIV_VALUE); + + + //Create clock divider using BUFGCE cells as the PLL/MMCM cannot generate clocks + //slower than 4.69 MHz and we need 32.768kHz + + logic [COUNTER_WIDTH-1:0] clk_counter_d, clk_counter_q; + logic clock_gate_en; + + logic intermmediate_clock; + + xilinx_slow_clk_mngr i_slow_clk_mngr + ( + .resetn(rst_ni), + .clk_in1(ref_clk_i), + .clk_out1(intermmediate_clock) + ); + + + + always_comb begin + if (clk_counter_q == CLK_DIV_VALUE-1) begin + clk_counter_d = '0; + clock_gate_en = 1'b1; + end else begin + clk_counter_d = clk_counter_q + 1; + clock_gate_en = 1'b0; + end + end + + always_ff @(posedge intermmediate_clock, negedge rst_ni) begin + if (!rst_ni) begin + clk_counter_q <= '0; + end else begin + clk_counter_q <= clk_counter_d; + end + end + + BUFGCE i_clock_gate + ( + .I(intermmediate_clock), + .CE(clock_gate_en), + .O(slow_clk_o) + ); + +endmodule : fpga_slow_clk_gen diff --git a/target/fpga/pulpissimo-zyboz7/rtl/pad_functional_xilinx.sv b/target/fpga/pulpissimo-zyboz7/rtl/pad_functional_xilinx.sv new file mode 100644 index 00000000..a3ca1cde --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/rtl/pad_functional_xilinx.sv @@ -0,0 +1,48 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + + +module pad_functional_pd +( + input logic OEN, + input logic I, + output logic O, + input logic PEN, + inout logic PAD +); + + (* PULLDOWN = "YES" *) + IOBUF iobuf_i ( + .T ( OEN ), + .I ( I ), + .O ( O ), + .IO( PAD ) + ); + +endmodule + +module pad_functional_pu +( + input logic OEN, + input logic I, + output logic O, + input logic PEN, + inout logic PAD +); + + (* PULLUP = "YES" *) + IOBUF iobuf_i ( + .T ( OEN ), + .I ( I ), + .O ( O ), + .IO( PAD ) + ); + +endmodule \ No newline at end of file diff --git a/target/fpga/pulpissimo-zyboz7/rtl/pulp_clock_gating_xilinx.sv b/target/fpga/pulpissimo-zyboz7/rtl/pulp_clock_gating_xilinx.sv new file mode 100644 index 00000000..e4974dae --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/rtl/pulp_clock_gating_xilinx.sv @@ -0,0 +1,27 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module pulp_clock_gating + ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o + ); + logic clk_en; + + // Use a latch based clock gate instead of BUFGCE. Otherwise we quickly run out of BUFGCTRL cells on the FPGAs. + always_latch begin + if (clk_i == 1'b0) clk_en <= en_i | test_en_i; + end + + assign clk_o = clk_i & clk_en; + +endmodule diff --git a/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v new file mode 100644 index 00000000..89f07e05 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v @@ -0,0 +1,161 @@ +//----------------------------------------------------------------------------- +// Title : PULPissimo Verilog Wrapper +//----------------------------------------------------------------------------- +// File : xilinx_pulpissimo.v +// Author : Manuel Eggimann +// : Marek PikuĊ‚a +// Created : 08.10.2019 +//----------------------------------------------------------------------------- +// Description : +// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2019 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + +module xilinx_pulpissimo ( + input wire ref_clk_i, + input wire pad_reset, + + output wire test_clk_o, + output wire obs1_o, + output wire obs2_o, + + // PMOD JE + inout wire pad_jtag_tck, + inout wire pad_jtag_tdi, + inout wire pad_jtag_tdo, + inout wire pad_jtag_tms, + + // PMOD JE + inout wire pad_uart_rx, + inout wire pad_uart_tx, + inout wire pad_uart_rts, + inout wire pad_uart_cts, + + inout wire led0_o, + inout wire led1_o, + inout wire led2_o, + inout wire led3_o, + + inout wire switch0_i, + inout wire switch1_i, + inout wire switch2_i, + inout wire switch3_i, + + // PMOD JC + inout wire pad_pmodc_1, + inout wire pad_pmodc_2, + inout wire pad_pmodc_3, + inout wire pad_pmodc_4, + inout wire pad_pmodc_7, + inout wire pad_pmodc_8, + inout wire pad_pmodc_9, + inout wire pad_pmodc_10, + + inout wire btn1_i, + inout wire btn2_i, + inout wire btn3_i, + + // PMOD JD + inout wire pad_pmodd_1, + + // PMOD JB + inout wire pad_pmodb_1, + inout wire pad_pmodb_2, + inout wire pad_pmodb_3, + inout wire pad_pmodb_4, + inout wire pad_pmodb_7, + inout wire pad_pmodb_8, + inout wire pad_pmodb_9, + inout wire pad_pmodb_10 +); + + localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + localparam USE_FPU = 1; + localparam USE_HWPE = 0; + + wire ref_clk_int; + wire rst_n; + assign rst_n = ~pad_reset; + + // Input clock buffer + BUFG i_sysclk_bufg ( + .I(ref_clk_i), + .O(ref_clk_int) + ); + + + // PULPissimo instance + pulpissimo #( + .CORE_TYPE(CORE_TYPE), + .USE_FPU(USE_FPU), + .USE_HWPE(USE_HWPE) + ) i_pulpissimo ( + .pad_ref_clk ( ref_clk_int ), + .pad_reset_n ( rst_n ), + .pad_clk_byp_en ( 1'b0 ), + + .pad_bootsel0 ( ), + .pad_bootsel1 ( ), + + .pad_jtag_tck ( pad_jtag_tck ), + .pad_jtag_tdi ( pad_jtag_tdi ), + .pad_jtag_tdo ( pad_jtag_tdo ), + .pad_jtag_tms ( pad_jtag_tms ), + .pad_jtag_trstn ( ), // Tied to 1 in run.tcl + + .pad_hyper_csn ( ), + .pad_hyper_reset_n ( ), + .pad_hyper_ck ( ), + .pad_hyper_ckn ( ), + .pad_hyper_dq ( ), + .pad_hyper_rwds ( ), + + .pad_io ( { + pad_pmodd_1, // io_31 + pad_pmodc_10, // io_30 + pad_pmodc_9, // io_29 + pad_pmodc_8, // io_28 + pad_pmodc_7, // io_27 + pad_pmodc_4, // io_26 + pad_pmodc_3, // io_25 + pad_pmodc_2, // io_24 + pad_pmodc_1, // io_23 + pad_pmodb_10, // io_22 + pad_pmodb_9, // io_21 + pad_pmodb_8, // io_20 + pad_pmodb_7, // io_19 + pad_pmodb_4, // io_18 + pad_pmodb_3, // io_17 + pad_pmodb_2, // io_16 + pad_pmodb_1, // io_15 + switch3_i, // io_14 + switch2_i, // io_13 + switch1_i, // io_12 + switch0_i, // io_11 + btn3_i, // io_10 + btn2_i, // io_09 + btn1_i, // io_08 + led3_o, // io_07 + led2_o, // io_06 + led1_o, // io_05 + led0_o, // io_04 + pad_uart_rts, // io_03 + pad_uart_cts, // io_02 + pad_uart_rx, // io_01 + pad_uart_tx // io_00 + } ), + .test_clk_o (test_clk_o), + .obs1_o (obs1_o), + .obs2_o (obs2_o) + ); + +endmodule diff --git a/target/fpga/pulpissimo-zyboz7/tcl/.gitignore b/target/fpga/pulpissimo-zyboz7/tcl/.gitignore new file mode 100644 index 00000000..587a0fa6 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/tcl/.gitignore @@ -0,0 +1,6 @@ +#Ignore tcl files generated by ipstools +ips_add_files.tcl +ips_inc_dirs.tcl +ips_src_files.tcl +rtl_add_files.tcl +rtl_src_files.tcl \ No newline at end of file diff --git a/target/fpga/pulpissimo-zyboz7/tcl/common.tcl b/target/fpga/pulpissimo-zyboz7/tcl/common.tcl new file mode 100644 index 00000000..f86dcbd0 --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/tcl/common.tcl @@ -0,0 +1,32 @@ +# detect board +if [info exists ::env(BOARD)] { + set BOARD $::env(BOARD) +} else { + puts "BOARD is not defined. Please include 'fpga-settings.mk' in your Makefile to setup necessary environment variables." + exit +} +if [info exists ::env(XILINX_BOARD)] { + set XILINX_BOARD $::env(XILINX_BOARD) +} +set partNumber $::env(XILINX_PART) + +set_param board.repoPaths /home/michaero/.Xilinx/Vivado/2023.2/xhub/board_store/xilinx_board_store + +# sets up Vivado messages in a more sensible way +set_msg_config -id {[Synth 8-3352]} -new_severity "critical warning" +set_msg_config -id {[Synth 8-350]} -new_severity "critical warning" +set_msg_config -id {[Synth 8-2490]} -new_severity "warning" +set_msg_config -id {[Synth 8-2306]} -new_severity "info" +set_msg_config -id {[Synth 8-3331]} -new_severity "critical warning" +set_msg_config -id {[Synth 8-3332]} -new_severity "info" +set_msg_config -id {[Synth 8-2715]} -new_severity "error" +set_msg_config -id {[Opt 31-35]} -new_severity "info" +set_msg_config -id {[Opt 31-32]} -new_severity "info" +set_msg_config -id {[Shape Builder 18-119]} -new_severity "warning" +set_msg_config -id {[Filemgmt 20-742]} -new_severity "error" + +# Set number of CPUs, default to 4 if system's getconf doesn't work +set CPUS [exec getconf _NPROCESSORS_ONLN] +if { ![info exists CPUS] } { + set CPUS 4 +} diff --git a/target/fpga/pulpissimo-zyboz7/tcl/download_bitstream.tcl b/target/fpga/pulpissimo-zyboz7/tcl/download_bitstream.tcl new file mode 100644 index 00000000..dab88c5f --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/tcl/download_bitstream.tcl @@ -0,0 +1,10 @@ +# required argument: path to bitstream file +open_hw_manager +connect_hw_server +open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost:*]] 0] +set device [lindex [get_hw_devices] 1] +set_property PROGRAM.FILE [lindex $argv 0] $device +set_property PROBES.FILE {} $device +# set_property FULL_PROBES.FILE {} $device +program_hw_devices $device +exit diff --git a/target/fpga/pulpissimo-zyboz7/tcl/run.tcl b/target/fpga/pulpissimo-zyboz7/tcl/run.tcl new file mode 100644 index 00000000..c19033ed --- /dev/null +++ b/target/fpga/pulpissimo-zyboz7/tcl/run.tcl @@ -0,0 +1,113 @@ +source tcl/common.tcl + +set PROJECT pulpissimo-$BOARD +set RTL ../../../rtl +set IPS ../../../ips +set CONSTRS constraints + +# create project +create_project $PROJECT . -force -part $::env(XILINX_PART) +set_property board_part $XILINX_BOARD [current_project] + +# Add sources +source ../pulpissimo/tcl/add_sources.tcl + +# Override IPSApprox default variables +set FPGA_RTL rtl +set FPGA_IPS ips + +# remove duplicate incompatible modules +# remove_files $IPS/pulp_soc/rtl/components/axi_slice_dc_slave_wrap.sv +# remove_file $IPS/pulp_soc/rtl/components/axi_slice_dc_master_wrap.sv +# remove_file $IPS/tech_cells_generic/pad_functional_xilinx.sv +# remove_file $IPS/riscv/rtl/riscv_ex_stage.sv + +# Set Verilog Defines. +set DEFINES "FPGA_TARGET_XILINX=1 PULP_FPGA_EMUL=1 AXI4_XCHECK_OFF=1" +if { $BOARD == "zyboz7" } { + set DEFINES "$DEFINES ZYBOZ7=1" +} +set_property verilog_define $DEFINES [current_fileset] + +# detect target clock +if [info exists ::env(FC_CLK_PERIOD_NS)] { + set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS) +} else { + set FC_CLK_PERIOD_NS 10.000 +} +set CLK_HALFPERIOD_NS [expr ${FC_CLK_PERIOD_NS} / 2.0] + +# Add toplevel wrapper +add_files -norecurse $FPGA_RTL/xilinx_pulpissimo.v + +# Add Xilinx IPs +read_ip $FPGA_IPS/xilinx_clk_mngr/xilinx_clk_mngr.srcs/sources_1/ip/xilinx_clk_mngr/xilinx_clk_mngr.xci +read_ip $FPGA_IPS/xilinx_slow_clk_mngr/xilinx_slow_clk_mngr.srcs/sources_1/ip/xilinx_slow_clk_mngr/xilinx_slow_clk_mngr.xci + +# Add wrappers and xilinx specific techcells +add_files -norecurse $FPGA_RTL/fpga_clk_gen.sv +add_files -norecurse $FPGA_RTL/fpga_slow_clk_gen.sv +add_files -norecurse $FPGA_RTL/fpga_bootrom.sv +add_files -norecurse $FPGA_RTL/pad_functional_xilinx.sv +add_files -norecurse $FPGA_RTL/pulp_clock_gating_xilinx.sv +add_files -norecurse $FPGA_RTL/cv32e40p_clock_gate_xilinx.sv + +# set pulpissimo as top +set_property top xilinx_pulpissimo [current_fileset]; # + +# needed only if used in batch mode +update_compile_order -fileset sources_1 + +# Add constraints +add_files -fileset constrs_1 -norecurse $CONSTRS/$BOARD.xdc + +# Elaborate design +synth_design -rtl -name rtl_1 -sfcu;# sfcu -> run synthesis in single file compilation unit mode + +# Launch synthesis +set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1] +set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value -sfcu -objects [get_runs synth_1] ;# Use single file compilation unit mode to prevent issues with import pkg::* statements in the codebase +launch_runs synth_1 -jobs $CPUS +wait_on_run synth_1 +open_run synth_1 -name netlist_1 +set_property needs_refresh false [get_runs synth_1] + +# Remove unused IOBUF cells in padframe (they are not optimized away since the +# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i) +# Disconnect the nets and connect them to ground to avoid issues in optimization +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_bootsel* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/bootsel_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_hyper* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/pad_to_hyper_i*] -net i_pulpissimo/ + +remove_cell i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_trst* +disconnect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] +connect_net -objects [get_nets i_pulpissimo/i_soc_domain/jtag_trst_ni] -net i_pulpissimo/ + + +# Launch Implementation + +# set for RuntimeOptimized implementation +set_property "steps.opt_design.args.directive" "RuntimeOptimized" [get_runs impl_1] +set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] +set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] + +set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1] + +launch_runs impl_1 -jobs $CPUS +wait_on_run impl_1 +launch_runs impl_1 -jobs $CPUS -to_step write_bitstream +wait_on_run impl_1 + +open_run impl_1 + +# Generate reports +exec mkdir -p reports/ +exec rm -rf reports/* +check_timing -file reports/$PROJECT.check_timing.rpt +report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$PROJECT.timing_WORST_100.rpt +report_timing -nworst 1 -delay_type max -sort_by group -file reports/$PROJECT.timing.rpt +report_utilization -hierarchical -file reports/$PROJECT.utilization.rpt From 24a83534ca74532385778a46e2dce705bfcae251 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Mon, 6 May 2024 00:31:13 +0200 Subject: [PATCH 02/27] Make vsim compilation properly stop at errors + update runtime for CV32E40X --- sw/pulp-runtime | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/pulp-runtime b/sw/pulp-runtime index ad0f614a..4c831baf 160000 --- a/sw/pulp-runtime +++ b/sw/pulp-runtime @@ -1 +1 @@ -Subproject commit ad0f614a1b805255cfe9cea9a563b5a434d8770a +Subproject commit 4c831baf80b18ec308ceef07375dbfa6322d4f76 From 0ab6d4effac6ae523054c560b3f8c349cb719114 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Mon, 6 May 2024 00:38:29 +0200 Subject: [PATCH 03/27] Add extremely preliminary FIR XIFU --- Bender.lock | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/Bender.lock b/Bender.lock index 2027f987..abcbb5b5 100644 --- a/Bender.lock +++ b/Bender.lock @@ -70,15 +70,16 @@ packages: source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] - cv32e40p: - revision: 7a49867b2232d97344cde1b8a1e05bcb38634894 - version: null + cv32e40x: + revision: 636785cd4aef6e857b320834b3ec158b2be7d2c8 + source: + Git: https://github.com/pulp-platform/cv32e40x.git + fir-xifu: + revision: 0fbc043db0798adbb3bec8ee37b7b08f010cce23 source: - Git: https://github.com/pulp-platform/cv32e40p.git + Git: https://iis-git.ee.ethz.ch/ades-labs/fir-xifu.git dependencies: - - common_cells - - fpnew - - tech_cells_generic + - cv32e40x fpnew: revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null @@ -169,7 +170,7 @@ packages: revision: bf65372aab4edd404160170e2a4d2c63b27ab5f2 version: 5.0.1 source: - Git: https://github.com/pulp-platform/pulp_soc.git + Git: https://github.com/pulp-platform/pulpissimo.git dependencies: - adv_dbg_if - apb @@ -179,7 +180,8 @@ packages: - axi - cluster_interconnect - common_cells - - cv32e40p + - cv32e40x + - fir-xifu - fpnew - hwpe-mac-engine - ibex @@ -264,8 +266,8 @@ packages: - tech_cells_generic - udma_core udma_core: - revision: 32bcc4f7472c3eeb8ef04612deb9088ffce7eb59 - version: 2.0.0 + revision: d032d4914e63924c9a6e51b11ab36efe36999e30 + version: null source: Git: https://github.com/pulp-platform/udma_core.git dependencies: From 5866b313b2b3b70fab25a821fcc1fbdce3e666d3 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Tue, 7 May 2024 07:33:12 +0200 Subject: [PATCH 04/27] Fix missing deps in manually hacked Bender.lock --- Bender.lock | 1 + 1 file changed, 1 insertion(+) diff --git a/Bender.lock b/Bender.lock index abcbb5b5..dafe9d69 100644 --- a/Bender.lock +++ b/Bender.lock @@ -74,6 +74,7 @@ packages: revision: 636785cd4aef6e857b320834b3ec158b2be7d2c8 source: Git: https://github.com/pulp-platform/cv32e40x.git + dependencies: [] fir-xifu: revision: 0fbc043db0798adbb3bec8ee37b7b08f010cce23 source: From 6af8d64f468a41f1e6ee2605a699689409bb7a57 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 20:16:58 +0200 Subject: [PATCH 05/27] Update Bender.lock, Bender.yml, Xilinx constraints, memory size. --- Bender.lock | 60 +++++++++++++------ Bender.yml | 2 +- hw/pulpissimo.sv | 2 +- target/fpga/Makefile | 13 ++++ .../pulpissimo-zyboz7/constraints/zyboz7.xdc | 12 +++- .../pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v | 9 +-- 6 files changed, 70 insertions(+), 28 deletions(-) diff --git a/Bender.lock b/Bender.lock index dafe9d69..5ee72ec0 100644 --- a/Bender.lock +++ b/Bender.lock @@ -71,14 +71,26 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cv32e40x: - revision: 636785cd4aef6e857b320834b3ec158b2be7d2c8 + revision: null + version: null source: - Git: https://github.com/pulp-platform/cv32e40x.git + Path: working_dir/cv32e40x dependencies: [] + fir-hwpe: + revision: null + version: null + source: + Path: working_dir/fir-hwpe + dependencies: + - hci + - hwpe-ctrl + - hwpe-stream + - zeroriscy fir-xifu: - revision: 0fbc043db0798adbb3bec8ee37b7b08f010cce23 + revision: null + version: null source: - Git: https://iis-git.ee.ethz.ch/ades-labs/fir-xifu.git + Path: working_dir/fir-xifu dependencies: - cv32e40x fpnew: @@ -114,26 +126,27 @@ packages: - common_verification - register_interface - tech_cells_generic - hwpe-ctrl: - revision: 1916c72f024175f1fe351acc3db3c6e9925a117d - version: 1.7.3 + hci: + revision: null + version: null source: - Git: https://github.com/pulp-platform/hwpe-ctrl.git + Path: working_dir/hci dependencies: - - tech_cells_generic - hwpe-mac-engine: - revision: cd48c574f1972ecbe02d3f463a0e12a92acde484 - version: 1.3.3 + - cluster_interconnect + - hwpe-stream + - l2_tcdm_hybrid_interco + hwpe-ctrl: + revision: 877d676329785f7bba042402e0a6f329a387573d + version: null source: - Git: https://github.com/pulp-platform/hwpe-mac-engine.git + Git: git@github.com:pulp-platform/hwpe-ctrl.git dependencies: - - hwpe-ctrl - - hwpe-stream + - tech_cells_generic hwpe-stream: revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 version: 1.8.0 source: - Git: https://github.com/pulp-platform/hwpe-stream.git + Git: git@github.com:pulp-platform/hwpe-stream.git dependencies: - tech_cells_generic ibex: @@ -149,6 +162,12 @@ packages: source: Git: https://github.com/pulp-platform/jtag_pulp.git dependencies: [] + l2_tcdm_hybrid_interco: + revision: fa55e72859dcfb117a2788a77352193bef94ff2b + version: 1.0.0 + source: + Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git + dependencies: [] pulp_io: revision: da6f8817b667f17973ecb19cb1e7aa4347108716 version: 0.1.0 @@ -171,7 +190,7 @@ packages: revision: bf65372aab4edd404160170e2a4d2c63b27ab5f2 version: 5.0.1 source: - Git: https://github.com/pulp-platform/pulpissimo.git + Path: working_dir/pulp_soc dependencies: - adv_dbg_if - apb @@ -182,6 +201,7 @@ packages: - cluster_interconnect - common_cells - cv32e40x + - fir-hwpe - fir-xifu - fpnew - hwpe-mac-engine @@ -331,3 +351,9 @@ packages: dependencies: - common_cells - udma_core + zeroriscy: + revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 + version: null + source: + Git: git@github.com:yvantor/ibex.git + dependencies: [] diff --git a/Bender.yml b/Bender.yml index 77782261..aac94620 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", version: 5.0.1 } + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "e507a97ab1e6e6c55d9c381418b2975cc0c62138" } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } diff --git a/hw/pulpissimo.sv b/hw/pulpissimo.sv index b09b12ac..9a1fc87b 100644 --- a/hw/pulpissimo.sv +++ b/hw/pulpissimo.sv @@ -39,7 +39,7 @@ module pulpissimo #( /// Standard RISC-V extension: Reuses the integer regfile for FPU usage instead of requiring a /// dedicated FPU regfile. Requires correct compiler settings for software to work! parameter bit USE_ZFINX = 1, - parameter bit USE_HWPE = 0, + parameter bit USE_HWPE = 1, /// Enable the virtual stdout interface for communication with simulated testbenches. This /// parameter must be disabled during any form of physical implementation. parameter bit SIM_STDOUT = 0, diff --git a/target/fpga/Makefile b/target/fpga/Makefile index 0d630891..651d1e0e 100644 --- a/target/fpga/Makefile +++ b/target/fpga/Makefile @@ -119,3 +119,16 @@ clean_zcu102: $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu102 clean rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bit rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bin + +## Generates the bistream for the zyboz7 board +zyboz7: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7 all + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7/pulpissimo-zyboz7.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bit + cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7/pulpissimo-zyboz7.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bin + @echo "Bitstream generation for zyboz7 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zyboz7.bit and ./pulpissimo_zyboz7.bin" + +## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zyboz7 board. +clean_zyboz7: + $(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7 clean + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bit + rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bin diff --git a/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc b/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc index e18cda6b..e1a1e9c8 100644 --- a/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc +++ b/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc @@ -19,6 +19,9 @@ create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_j set_input_jitter tck 1.000 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O] +# generated clocks +create_generated_clock -source [get_ports ref_clk_i] [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_in1] +create_generated_clock -source [get_ports ref_clk_i] [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_in1] # minimize routing delay set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi] @@ -30,9 +33,9 @@ set_max_delay -from [get_ports pad_jtag_tms] 20.000 set_max_delay -from [get_ports pad_jtag_tdi] 20.000 set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 - +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/jtag_tap_top_i/confreg/reg_bit_last/r_dataout_reg/C] -to [get_pins i_pulpissimo/i_clock_gen/i_slow_clk_bypass_mux/i_BUFGMUX/I1] 20.000 # reset signal set_false_path -from [get_ports pad_reset] @@ -64,6 +67,9 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \ -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] +# waive DRCs related to emulated clock gating cells +create_waiver -of_objects [get_methodology_violations -name xilinx_pulpissimo_methodology_drc_routed.rpx {TIMING-14#1}] -user fconti -description {emulated clock gating cells} + ############################################################# # _____ ____ _____ _ _ _ # # |_ _/ __ \ / ____| | | | | (_) # diff --git a/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v index 89f07e05..5861ef6e 100644 --- a/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v @@ -79,8 +79,8 @@ module xilinx_pulpissimo ( ); localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - localparam USE_FPU = 1; - localparam USE_HWPE = 0; + localparam USE_FPU = 0; + localparam USE_HWPE = 1; wire ref_clk_int; wire rst_n; @@ -152,10 +152,7 @@ module xilinx_pulpissimo ( pad_uart_cts, // io_02 pad_uart_rx, // io_01 pad_uart_tx // io_00 - } ), - .test_clk_o (test_clk_o), - .obs1_o (obs1_o), - .obs2_o (obs2_o) + } ) ); endmodule From 4ae9651ff8e6f7dcf7ad04696f9314136d7df8ca Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 20:33:51 +0200 Subject: [PATCH 06/27] Fix Bender.lock --- Bender.lock | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/Bender.lock b/Bender.lock index 5ee72ec0..d5eda469 100644 --- a/Bender.lock +++ b/Bender.lock @@ -71,26 +71,26 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cv32e40x: - revision: null + revision: 636785cd4aef6e857b320834b3ec158b2be7d2c8 version: null source: - Path: working_dir/cv32e40x + Git: https://github.com/pulp-platform/cv32e40x.git dependencies: [] fir-hwpe: - revision: null + revision: 1b7c0c43c1e32be61e54f6eee95ccd94cb2541c6 version: null source: - Path: working_dir/fir-hwpe + Git: git@iis-git.ee.ethz.ch:ades-labs/fir-hwpe.git dependencies: - hci - hwpe-ctrl - hwpe-stream - zeroriscy fir-xifu: - revision: null + revision: 2491bd2ac4ec1c45fc08dcb1f964ae6f520e29da version: null source: - Path: working_dir/fir-xifu + Git: git@iis-git.ee.ethz.ch:ades-labs/fir-xifu.git dependencies: - cv32e40x fpnew: @@ -127,10 +127,10 @@ packages: - register_interface - tech_cells_generic hci: - revision: null + revision: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 version: null source: - Path: working_dir/hci + Git: git@github.com:pulp-platform/hci.git dependencies: - cluster_interconnect - hwpe-stream @@ -187,10 +187,10 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: bf65372aab4edd404160170e2a4d2c63b27ab5f2 - version: 5.0.1 + revision: e507a97ab1e6e6c55d9c381418b2975cc0c62138 + version: null source: - Path: working_dir/pulp_soc + Git: https://github.com/pulp-platform/pulp_soc.git dependencies: - adv_dbg_if - apb From 313a2d9d4a01a5b81e1b375867aa5c8440f8c330 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 20:40:57 +0200 Subject: [PATCH 07/27] Use deps in GitHub only --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index aac94620..ca10ce0e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "e507a97ab1e6e6c55d9c381418b2975cc0c62138" } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "a0661ddd06286ba409a2c3c67eb58fba5c559026" } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From 5f9c9927ae808a80e9095c2b2da94a5d87b37c94 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 22:53:49 +0200 Subject: [PATCH 08/27] Fix Bender.lock manually --- Bender.lock | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index d5eda469..47890c37 100644 --- a/Bender.lock +++ b/Bender.lock @@ -80,7 +80,7 @@ packages: revision: 1b7c0c43c1e32be61e54f6eee95ccd94cb2541c6 version: null source: - Git: git@iis-git.ee.ethz.ch:ades-labs/fir-hwpe.git + Git: https://github.com/pulp-platform/fir-hwpe.git dependencies: - hci - hwpe-ctrl @@ -90,7 +90,7 @@ packages: revision: 2491bd2ac4ec1c45fc08dcb1f964ae6f520e29da version: null source: - Git: git@iis-git.ee.ethz.ch:ades-labs/fir-xifu.git + Git: https://github.com/pulp-platform/fir-xifu.git dependencies: - cv32e40x fpnew: From cb455fed49abb5e6efb58eb4060012020d600f4e Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Wed, 15 May 2024 22:16:30 +0200 Subject: [PATCH 09/27] Update Bender + update runtime + add minimal test for XIFU --- Bender.lock | 4 ++-- Bender.yml | 2 +- sw/regression_tests | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 47890c37..a262e28d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -87,7 +87,7 @@ packages: - hwpe-stream - zeroriscy fir-xifu: - revision: 2491bd2ac4ec1c45fc08dcb1f964ae6f520e29da + revision: 36abd2f98a809dc6cc70ffe008bd59555a8ef51b version: null source: Git: https://github.com/pulp-platform/fir-xifu.git @@ -187,7 +187,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: e507a97ab1e6e6c55d9c381418b2975cc0c62138 + revision: 8a821b6cbf45cda5f1b2ce67cf6c04ffa8e1fa27 version: null source: Git: https://github.com/pulp-platform/pulp_soc.git diff --git a/Bender.yml b/Bender.yml index ca10ce0e..597e253e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "a0661ddd06286ba409a2c3c67eb58fba5c559026" } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "8a821b6cbf45cda5f1b2ce67cf6c04ffa8e1fa27" } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } diff --git a/sw/regression_tests b/sw/regression_tests index eae705b1..ca86e060 160000 --- a/sw/regression_tests +++ b/sw/regression_tests @@ -1 +1 @@ -Subproject commit eae705b1b0094a5619b7d9d3b37f5050f5abc398 +Subproject commit ca86e060dc5b119277a2d23e9aff5467c61d0441 From 8abe60ab58b0ebcd22bcfb078ca5bbd72f5af279 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Wed, 15 May 2024 22:57:34 +0200 Subject: [PATCH 10/27] Add symlinks to FIR HWPE & XIFU + CV32E40X + pulp_soc to deps folder --- Bender.yml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index 597e253e..15c358f6 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "8a821b6cbf45cda5f1b2ce67cf6c04ffa8e1fa27" } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "a0661ddd06286ba409a2c3c67eb58fba5c559026" } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } @@ -78,6 +78,12 @@ sources: - target/sim/tb/tb_pulp.sv - target/sim/tb/tb_pulp_simple.sv +workspace: + package_links: + deps/cv32e40x: cv32e40x + deps/fir-hwpe: fir-hwpe + deps/pulp_soc: pulp_soc + deps/fir-xifu: fir-xifu vendor_package: # Import the GPIO repository directly. Since we have to regenerate the RTL From ba79d88d96ff3bde0f1710644807a82dab18a4ad Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Thu, 16 May 2024 00:18:07 +0200 Subject: [PATCH 11/27] Update Bender.yml/lock with beautified pulp_soc --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index a262e28d..4ab2825c 100644 --- a/Bender.lock +++ b/Bender.lock @@ -187,7 +187,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: 8a821b6cbf45cda5f1b2ce67cf6c04ffa8e1fa27 + revision: e3fa9100629b87834f7da8d494e8d58f3cb24080 version: null source: Git: https://github.com/pulp-platform/pulp_soc.git diff --git a/Bender.yml b/Bender.yml index 15c358f6..3d6a89f8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "a0661ddd06286ba409a2c3c67eb58fba5c559026" } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "e3fa9100629b87834f7da8d494e8d58f3cb24080" } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From 14a62aeaa4695e03bf8e7eb58b2011bbdda3f984 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Thu, 16 May 2024 00:46:37 +0200 Subject: [PATCH 12/27] In this branch, use CORE_TYPE=3 (CV32E40X) --- hw/pulpissimo.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/pulpissimo.sv b/hw/pulpissimo.sv index 9a1fc87b..424343f6 100644 --- a/hw/pulpissimo.sv +++ b/hw/pulpissimo.sv @@ -29,8 +29,8 @@ module pulpissimo #( /// 0 for CV32E40P with XPULP Extensions, 1 for IBEX RV32IMC (formerly ZERORISCY), - /// 2 for IBEX RV32EC (formerly MICRORISCY) - parameter int unsigned CORE_TYPE = 0, + /// 2 for IBEX RV32EC (formerly MICRORISCY), 3 for CV32E40X + parameter int unsigned CORE_TYPE = 3, /// Enable XPULP extensions on CV32E40P. Has no effect if an IBEX core variant is use. parameter bit USE_XPULP = 1, /// Mutually exclusive with the use of IBEX. I.e. if an IBEX core variant is used, this parameter From e69a94998d141ce43472b27357559187075a69a1 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Thu, 16 May 2024 00:48:21 +0200 Subject: [PATCH 13/27] Update pulp_soc version --- Bender.lock | 12 +++++++++++- Bender.yml | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 4ab2825c..f6e291c8 100644 --- a/Bender.lock +++ b/Bender.lock @@ -70,6 +70,15 @@ packages: source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] + cv32e40p: + revision: 7a49867b2232d97344cde1b8a1e05bcb38634894 + version: null + source: + Git: https://github.com/pulp-platform/cv32e40p.git + dependencies: + - common_cells + - fpnew + - tech_cells_generic cv32e40x: revision: 636785cd4aef6e857b320834b3ec158b2be7d2c8 version: null @@ -187,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: e3fa9100629b87834f7da8d494e8d58f3cb24080 + revision: 5ae7869970165483db776c0dec97103a07d00f6d version: null source: Git: https://github.com/pulp-platform/pulp_soc.git @@ -200,6 +209,7 @@ packages: - axi - cluster_interconnect - common_cells + - cv32e40p - cv32e40x - fir-hwpe - fir-xifu diff --git a/Bender.yml b/Bender.yml index 3d6a89f8..fd405321 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "e3fa9100629b87834f7da8d494e8d58f3cb24080" } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "5ae7869970165483db776c0dec97103a07d00f6d" } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From 4d6b4950ac344b7959c7458788a701034cb08652 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Thu, 16 May 2024 00:53:37 +0200 Subject: [PATCH 14/27] Fix pulp_soc --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index f6e291c8..6a33c6ad 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: 5ae7869970165483db776c0dec97103a07d00f6d + revision: 90db30b1267ac0995ebe91622e3046a2c0155987 version: null source: Git: https://github.com/pulp-platform/pulp_soc.git diff --git a/Bender.yml b/Bender.yml index fd405321..a2aef76e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "5ae7869970165483db776c0dec97103a07d00f6d" } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "90db30b1267ac0995ebe91622e3046a2c0155987" } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From 2dd3062e9248efa08072d671e1d18f623110eb43 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Thu, 16 May 2024 00:57:03 +0200 Subject: [PATCH 15/27] Fix defaults to CV32E40X in the right places --- hw/pulpissimo.sv | 2 +- target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v | 2 +- target/sim/tb/tb_pulp.sv | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/pulpissimo.sv b/hw/pulpissimo.sv index 424343f6..e85c0679 100644 --- a/hw/pulpissimo.sv +++ b/hw/pulpissimo.sv @@ -30,7 +30,7 @@ module pulpissimo #( /// 0 for CV32E40P with XPULP Extensions, 1 for IBEX RV32IMC (formerly ZERORISCY), /// 2 for IBEX RV32EC (formerly MICRORISCY), 3 for CV32E40X - parameter int unsigned CORE_TYPE = 3, + parameter int unsigned CORE_TYPE = 0, /// Enable XPULP extensions on CV32E40P. Has no effect if an IBEX core variant is use. parameter bit USE_XPULP = 1, /// Mutually exclusive with the use of IBEX. I.e. if an IBEX core variant is used, this parameter diff --git a/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v index 5861ef6e..b06dc791 100644 --- a/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-zyboz7/rtl/xilinx_pulpissimo.v @@ -78,7 +78,7 @@ module xilinx_pulpissimo ( inout wire pad_pmodb_10 ); - localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + localparam CORE_TYPE = 3; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY), 3 for CV32E40X localparam USE_FPU = 0; localparam USE_HWPE = 1; diff --git a/target/sim/tb/tb_pulp.sv b/target/sim/tb/tb_pulp.sv index ebad1770..b03ceefb 100644 --- a/target/sim/tb/tb_pulp.sv +++ b/target/sim/tb/tb_pulp.sv @@ -24,8 +24,8 @@ module tb_pulp; // simulation platform parameters - // Choose your core: 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - parameter CORE_TYPE = 0; + // Choose your core: 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY), 3 for CV32E40X + parameter CORE_TYPE = 3; // if RI5CY is instantiated (CORE_TYPE == 0), USE_FPU enables the FPU parameter USE_FPU = 1; From 5e85bd32423d0e08797b769723f5c4efb083a1e0 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sun, 19 May 2024 23:58:54 +0200 Subject: [PATCH 16/27] Adapt to LLVM-based setup + tracing in CV32E40X --- Bender.lock | 8 ++++---- Bender.yml | 2 +- target/sim/questasim/Makefile | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index 6a33c6ad..6862e8e2 100644 --- a/Bender.lock +++ b/Bender.lock @@ -80,7 +80,7 @@ packages: - fpnew - tech_cells_generic cv32e40x: - revision: 636785cd4aef6e857b320834b3ec158b2be7d2c8 + revision: fe5e7f41ad284b5aee583a727503bb6f1097daab version: null source: Git: https://github.com/pulp-platform/cv32e40x.git @@ -96,8 +96,8 @@ packages: - hwpe-stream - zeroriscy fir-xifu: - revision: 36abd2f98a809dc6cc70ffe008bd59555a8ef51b - version: null + revision: b31bc66683704646727140b57a91c5ca2de396d5 + version: 0.1.0 source: Git: https://github.com/pulp-platform/fir-xifu.git dependencies: @@ -196,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: 90db30b1267ac0995ebe91622e3046a2c0155987 + revision: 7c377ca63b5d792a99605a26cafd487863c85df0 version: null source: Git: https://github.com/pulp-platform/pulp_soc.git diff --git a/Bender.yml b/Bender.yml index a2aef76e..658b01d0 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "90db30b1267ac0995ebe91622e3046a2c0155987" } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.1.1 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } diff --git a/target/sim/questasim/Makefile b/target/sim/questasim/Makefile index 9adefd2f..a3d326bc 100644 --- a/target/sim/questasim/Makefile +++ b/target/sim/questasim/Makefile @@ -19,7 +19,7 @@ QUESTA_BUILD_DIR = $(PULPISSIMO_ROOT)/build/questasim include $(PULPISSIMO_ROOT)/utils/utils.mk ## Configuration Variables for Bender, Questasim behavior -BENDER_SCRIPTS_ARGS += -t rtl -t test -t rtl_sim +BENDER_SCRIPTS_ARGS += -t rtl -t test -t rtl_sim -t cv32e40x_bhv BENDER_VIP_SCRIPT_ARGS ?= -t rt_dpi -t i2c_vip -t flash_vip -t i2s_vip -t use_vips VSIM_ARGS ?= -64 VLOG_ARGS += -suppress 2583 -suppress 13314 \"+incdir+\$$ROOT/hw/includes\" From d97c5da3d7633c03db3dab68423d597759481070 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sun, 19 May 2024 23:59:23 +0200 Subject: [PATCH 17/27] Log all signals automatically in QuestaSim --- target/sim/questasim/tcl_files/run.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/target/sim/questasim/tcl_files/run.tcl b/target/sim/questasim/tcl_files/run.tcl index 44f6cfd9..6c88a0f1 100644 --- a/target/sim/questasim/tcl_files/run.tcl +++ b/target/sim/questasim/tcl_files/run.tcl @@ -3,3 +3,4 @@ set TB "vopt_tb" source ./tcl_files/config/vsim.tcl +add log -r /* From 4df67b1efec296415d2369f6b5595471d0d36347 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Wed, 22 May 2024 23:37:32 +0200 Subject: [PATCH 18/27] Update versions + tests, working XIFU --- Bender.lock | 6 +++--- Bender.yml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 6862e8e2..b9c634d5 100644 --- a/Bender.lock +++ b/Bender.lock @@ -96,8 +96,8 @@ packages: - hwpe-stream - zeroriscy fir-xifu: - revision: b31bc66683704646727140b57a91c5ca2de396d5 - version: 0.1.0 + revision: 031d31f52f6c3151c5ff683e3e268277f2ddc30b + version: 0.1.1 source: Git: https://github.com/pulp-platform/fir-xifu.git dependencies: @@ -196,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: 7c377ca63b5d792a99605a26cafd487863c85df0 + revision: a9c360697d8f4cbf7859f2b52c9372d2a1945683 version: null source: Git: https://github.com/pulp-platform/pulp_soc.git diff --git a/Bender.yml b/Bender.yml index 658b01d0..94430c9a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.1.1 } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.1.2 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From ea4e376881a11b6dc3e1b7c1a6420662a499be57 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Thu, 23 May 2024 15:17:51 +0200 Subject: [PATCH 19/27] remove ssh from Bender.lock and .yml --- Bender.lock | 18 +++++++++--------- Bender.yml | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Bender.lock b/Bender.lock index b9c634d5..dbf7283e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -86,8 +86,8 @@ packages: Git: https://github.com/pulp-platform/cv32e40x.git dependencies: [] fir-hwpe: - revision: 1b7c0c43c1e32be61e54f6eee95ccd94cb2541c6 - version: null + revision: b59edc4daf6fc44b4c0b3bb8a494351299c0423a + version: 2.0.0 source: Git: https://github.com/pulp-platform/fir-hwpe.git dependencies: @@ -96,8 +96,8 @@ packages: - hwpe-stream - zeroriscy fir-xifu: - revision: 031d31f52f6c3151c5ff683e3e268277f2ddc30b - version: 0.1.1 + revision: 6ad47bd94458e2ace0d2976d92da4ba5d06268fb + version: 0.1.2 source: Git: https://github.com/pulp-platform/fir-xifu.git dependencies: @@ -139,7 +139,7 @@ packages: revision: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 version: null source: - Git: git@github.com:pulp-platform/hci.git + Git: https://github.com/pulp-platform/hci.git dependencies: - cluster_interconnect - hwpe-stream @@ -148,14 +148,14 @@ packages: revision: 877d676329785f7bba042402e0a6f329a387573d version: null source: - Git: git@github.com:pulp-platform/hwpe-ctrl.git + Git: https://github.com/pulp-platform/hwpe-ctrl.git dependencies: - tech_cells_generic hwpe-stream: revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 version: 1.8.0 source: - Git: git@github.com:pulp-platform/hwpe-stream.git + Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: - tech_cells_generic ibex: @@ -196,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: a9c360697d8f4cbf7859f2b52c9372d2a1945683 + revision: 40be30a32f1561958d873d9d82a9bb8ad14145aa version: null source: Git: https://github.com/pulp-platform/pulp_soc.git @@ -365,5 +365,5 @@ packages: revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 version: null source: - Git: git@github.com:yvantor/ibex.git + Git: https://github.com/yvantor/ibex.git dependencies: [] diff --git a/Bender.yml b/Bender.yml index 94430c9a..3bf187d8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.1.2 } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.1.4 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From 41d95353deeec2f437a01dd064f39290addd6984 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sun, 26 May 2024 00:51:45 +0200 Subject: [PATCH 20/27] Realign Bender + sw submodules after rebase (to check) --- Bender.lock | 7 +++---- Bender.yml | 2 +- sw/pulp-runtime | 2 +- sw/regression_tests | 2 +- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/Bender.lock b/Bender.lock index dbf7283e..967792b1 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: 40be30a32f1561958d873d9d82a9bb8ad14145aa + revision: d4b558f00a0ce6fa87bbf38190178e6003e9c81f version: null source: Git: https://github.com/pulp-platform/pulp_soc.git @@ -214,7 +214,6 @@ packages: - fir-hwpe - fir-xifu - fpnew - - hwpe-mac-engine - ibex - jtag_pulp - pulp_io @@ -297,8 +296,8 @@ packages: - tech_cells_generic - udma_core udma_core: - revision: d032d4914e63924c9a6e51b11ab36efe36999e30 - version: null + revision: 32bcc4f7472c3eeb8ef04612deb9088ffce7eb59 + version: 2.0.0 source: Git: https://github.com/pulp-platform/udma_core.git dependencies: diff --git a/Bender.yml b/Bender.yml index 3bf187d8..1d4d0ca1 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.1.4 } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.0 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } diff --git a/sw/pulp-runtime b/sw/pulp-runtime index 4c831baf..bbabedb3 160000 --- a/sw/pulp-runtime +++ b/sw/pulp-runtime @@ -1 +1 @@ -Subproject commit 4c831baf80b18ec308ceef07375dbfa6322d4f76 +Subproject commit bbabedb392ffc643b0c91a943f364a40a9decb47 diff --git a/sw/regression_tests b/sw/regression_tests index ca86e060..3cdc0bf3 160000 --- a/sw/regression_tests +++ b/sw/regression_tests @@ -1 +1 @@ -Subproject commit ca86e060dc5b119277a2d23e9aff5467c61d0441 +Subproject commit 3cdc0bf39c658b69af452cc2c72d89f66c2a3475 From c8005886f319a06f724aa2cc31cad088bc17c638 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sun, 26 May 2024 00:56:33 +0200 Subject: [PATCH 21/27] Update pulp_soc --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 967792b1..34386d17 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: d4b558f00a0ce6fa87bbf38190178e6003e9c81f + revision: 9e52068118f58a9fb035001c9f5f12c844d9299e version: null source: Git: https://github.com/pulp-platform/pulp_soc.git diff --git a/Bender.yml b/Bender.yml index 1d4d0ca1..2cb36cfa 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.0 } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.1 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From c0edc2d567531155fd076f7b8071d4e0b2ad461d Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 31 May 2024 16:33:24 +0200 Subject: [PATCH 22/27] Fix potential (?) syntax error on some machines --- target/sim/tb/tb_pulp.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sim/tb/tb_pulp.sv b/target/sim/tb/tb_pulp.sv index b03ceefb..e72a3a5c 100644 --- a/target/sim/tb/tb_pulp.sv +++ b/target/sim/tb/tb_pulp.sv @@ -16,9 +16,9 @@ module tb_pulp; - import srec_pkg::*; timeunit 1ns; timeprecision 100ps; + import srec_pkg::*; parameter CONFIG_FILE = "NONE"; From c6a54d43448dfd5ddcc6e492b378083e77c4f2d8 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 31 May 2024 17:16:10 +0200 Subject: [PATCH 23/27] Update fir-xifu (and pulp_soc) --- Bender.lock | 6 +++--- Bender.yml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 34386d17..ef42c996 100644 --- a/Bender.lock +++ b/Bender.lock @@ -96,8 +96,8 @@ packages: - hwpe-stream - zeroriscy fir-xifu: - revision: 6ad47bd94458e2ace0d2976d92da4ba5d06268fb - version: 0.1.2 + revision: 2b1a71fa7310c20ae0824b93669766713ebcec88 + version: 0.1.3 source: Git: https://github.com/pulp-platform/fir-xifu.git dependencies: @@ -196,7 +196,7 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: 9e52068118f58a9fb035001c9f5f12c844d9299e + revision: c339e2ea69ad6d22daefe19a9140c48f72a5d46b version: null source: Git: https://github.com/pulp-platform/pulp_soc.git diff --git a/Bender.yml b/Bender.yml index 2cb36cfa..e5e198f1 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.1 } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.2 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } From 39b48ff4e9fe560f57ea996c840d79b031e80646 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 26 Jul 2024 15:45:39 +0200 Subject: [PATCH 24/27] Add synthesis dependencies --- Bender.lock | 50 +++++++++++++++++++++++++++++++------------------- Bender.yml | 13 ++++--------- Makefile | 1 + 3 files changed, 36 insertions(+), 28 deletions(-) diff --git a/Bender.lock b/Bender.lock index ef42c996..36e46857 100644 --- a/Bender.lock +++ b/Bender.lock @@ -41,8 +41,8 @@ packages: - apb - common_cells axi: - revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 - version: 0.39.3 + revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7 + version: 0.39.4 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -57,8 +57,8 @@ packages: dependencies: - common_cells common_cells: - revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 - version: 1.35.0 + revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb + version: 1.37.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -80,28 +80,28 @@ packages: - fpnew - tech_cells_generic cv32e40x: - revision: fe5e7f41ad284b5aee583a727503bb6f1097daab + revision: null version: null source: - Git: https://github.com/pulp-platform/cv32e40x.git + Path: working_dir/cv32e40x dependencies: [] + decimate-xifu: + revision: null + version: null + source: + Path: working_dir/decimate-xifu + dependencies: + - cv32e40x fir-hwpe: - revision: b59edc4daf6fc44b4c0b3bb8a494351299c0423a - version: 2.0.0 + revision: null + version: null source: - Git: https://github.com/pulp-platform/fir-hwpe.git + Path: working_dir/fir-hwpe dependencies: - hci - hwpe-ctrl - hwpe-stream - zeroriscy - fir-xifu: - revision: 2b1a71fa7310c20ae0824b93669766713ebcec88 - version: 0.1.3 - source: - Git: https://github.com/pulp-platform/fir-xifu.git - dependencies: - - cv32e40x fpnew: revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null @@ -196,10 +196,10 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: c339e2ea69ad6d22daefe19a9140c48f72a5d46b + revision: null version: null source: - Git: https://github.com/pulp-platform/pulp_soc.git + Path: working_dir/pulp_soc dependencies: - adv_dbg_if - apb @@ -211,8 +211,8 @@ packages: - common_cells - cv32e40p - cv32e40x + - decimate-xifu - fir-hwpe - - fir-xifu - fpnew - ibex - jtag_pulp @@ -222,6 +222,12 @@ packages: - scm - tech_cells_generic - timer_unit + pulpissimo_essentials: + revision: null + version: null + source: + Path: working_dir/pulpissimo_essentials + dependencies: [] pulpissimo_optional_vips: revision: null version: null @@ -281,6 +287,12 @@ packages: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: - common_verification + tech_cells_gf22fdx: + revision: a1e4e0485afeefb905d8120b27503bf691c45725 + version: null + source: + Git: git@iis-git.ee.ethz.ch:pulp-restricted/tech_cells_GF22FDX.git + dependencies: [] timer_unit: revision: 4c69615c89db9397a9747d6f6d6a36727854f0bc version: 1.0.3 diff --git a/Bender.yml b/Bender.yml index e5e198f1..fa23cb92 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,6 +19,8 @@ dependencies: pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.2 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } + tech_cells_synthesis: { path: "target/gf22fdx/bender/tech_cells" } + pulpissimo_essentials: { path: "target/gf22fdx/bender/pulpissimo_essentials" } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } pulpissimo_padframe_fpga: { path: "hw/padframe/pulpissimo_padframe_fpga_autogen" } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } @@ -49,8 +51,8 @@ sources: - target: not(any(fpga, xilinx)) files: - hw/asic_autogen_rom.sv - - hw/soc_domain.sv - - hw/pulpissimo.sv + - hw/soc_domain.sv + - hw/pulpissimo.sv # rtl_sim - Generic version of pulpissimo used for non-verilator RTL simulation @@ -78,13 +80,6 @@ sources: - target/sim/tb/tb_pulp.sv - target/sim/tb/tb_pulp_simple.sv -workspace: - package_links: - deps/cv32e40x: cv32e40x - deps/fir-hwpe: fir-hwpe - deps/pulp_soc: pulp_soc - deps/fir-xifu: fir-xifu - vendor_package: # Import the GPIO repository directly. Since we have to regenerate the RTL # when we change the number GPIOs we cannot just depend on it as a regular diff --git a/Makefile b/Makefile index bb73cea0..133e9020 100644 --- a/Makefile +++ b/Makefile @@ -25,6 +25,7 @@ endif include target/sim/questasim/Makefile include target/lint/spyglass/Makefile include target/fpga/Makefile +include target/gf22fdx/synopsys/Makefile include $(PULPISSIMO_ROOT)/utils/utils.mk .PHONY: checkout From 0fa54bc7752ebf788f691c9943f88dbfd4d937d9 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 26 Jul 2024 17:50:59 +0200 Subject: [PATCH 25/27] Improvements to ease non-free synthesis flow --- Bender.lock | 36 ++++++++++++++++++------------------ Bender.yml | 7 ++++--- Makefile | 9 ++++++++- 3 files changed, 30 insertions(+), 22 deletions(-) diff --git a/Bender.lock b/Bender.lock index 36e46857..177ccce8 100644 --- a/Bender.lock +++ b/Bender.lock @@ -80,28 +80,28 @@ packages: - fpnew - tech_cells_generic cv32e40x: - revision: null + revision: fe5e7f41ad284b5aee583a727503bb6f1097daab version: null source: - Path: working_dir/cv32e40x + Git: https://github.com/pulp-platform/cv32e40x.git dependencies: [] - decimate-xifu: - revision: null - version: null - source: - Path: working_dir/decimate-xifu - dependencies: - - cv32e40x fir-hwpe: - revision: null - version: null + revision: 0397301c727e2f232e0f508fbdc13401c023fa26 + version: 2.0.2 source: - Path: working_dir/fir-hwpe + Git: https://github.com/pulp-platform/fir-hwpe.git dependencies: - hci - hwpe-ctrl - hwpe-stream - zeroriscy + fir-xifu: + revision: 2b1a71fa7310c20ae0824b93669766713ebcec88 + version: 0.1.3 + source: + Git: https://github.com/pulp-platform/fir-xifu.git + dependencies: + - cv32e40x fpnew: revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null @@ -196,10 +196,10 @@ packages: - udma_sdio - udma_uart pulp_soc: - revision: null + revision: 8c6b9dea6ba8dbdbc995efb6e0e24194d470f373 version: null source: - Path: working_dir/pulp_soc + Git: https://github.com/pulp-platform/pulp_soc.git dependencies: - adv_dbg_if - apb @@ -211,8 +211,8 @@ packages: - common_cells - cv32e40p - cv32e40x - - decimate-xifu - fir-hwpe + - fir-xifu - fpnew - ibex - jtag_pulp @@ -226,7 +226,7 @@ packages: revision: null version: null source: - Path: working_dir/pulpissimo_essentials + Path: target/synthesis/bender/pulpissimo_essentials dependencies: [] pulpissimo_optional_vips: revision: null @@ -288,10 +288,10 @@ packages: dependencies: - common_verification tech_cells_gf22fdx: - revision: a1e4e0485afeefb905d8120b27503bf691c45725 + revision: null version: null source: - Git: git@iis-git.ee.ethz.ch:pulp-restricted/tech_cells_GF22FDX.git + Path: target/synthesis/bender/tech_cells dependencies: [] timer_unit: revision: 4c69615c89db9397a9747d6f6d6a36727854f0bc diff --git a/Bender.yml b/Bender.yml index fa23cb92..6e43b208 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,16 +16,17 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } - pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.2 } # branch fc/cv32e40x + pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: efcl_ss-v0.2.4 } # branch fc/cv32e40x tbtools: { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - tech_cells_synthesis: { path: "target/gf22fdx/bender/tech_cells" } - pulpissimo_essentials: { path: "target/gf22fdx/bender/pulpissimo_essentials" } pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" } pulpissimo_padframe_fpga: { path: "hw/padframe/pulpissimo_padframe_fpga_autogen" } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } generic_FLL: { git: "https://github.com/pulp-platform/generic_FLL.git", version: 0.2.0 } apb_fll_if: { git: "https://github.com/pulp-platform/apb_fll_if.git", version: 0.2.1 } + # the following dependencies are non-free, and will be ignored in a free setup + tech_cells_gf22fdx: { path: "target/synthesis/bender/tech_cells" } + pulpissimo_essentials: { path: "target/synthesis/bender/pulpissimo_essentials" } # Target Specific Dependencies diff --git a/Makefile b/Makefile index 133e9020..b86021c9 100644 --- a/Makefile +++ b/Makefile @@ -25,14 +25,21 @@ endif include target/sim/questasim/Makefile include target/lint/spyglass/Makefile include target/fpga/Makefile -include target/gf22fdx/synopsys/Makefile include $(PULPISSIMO_ROOT)/utils/utils.mk +# ignore synthesis targets if only free setup available +-include target/synthesis/Makefile + .PHONY: checkout ## Checkout all Bender IPs checkout: $(PULPISSIMO_UTILS)/bender $(PULPISSIMO_UTILS)/bender checkout +.PHONY: checkout-synthesis +checkout-synthesis: + git clone --recursive git@iis-git.ee.ethz.ch:pulp-restricted/pulpissimo-synthesis target/synthesis + $(PULPISSIMO_UTILS)/bender update + .PHONY: hw bootrom padframe ## Re-generate generated hardware IPs hw: bootrom padframe From be268ec8807295551f83c332776609eb1cf20a84 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 27 Jul 2024 00:06:16 +0200 Subject: [PATCH 26/27] point CI to LLVM (currently, EFCL Summer School version) in this branch --- .gitlab-ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e028726c..2a300032 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -17,8 +17,8 @@ variables: QUESTA: "questa-2023.4-zr" VSIM: "$QUESTA vsim" VSIM_BIN: "$QUESTA vsim" - RISCV: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0" - PULP_RISCV_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0" + RISCV: "/usr/pack/riscv-1.0-kgf/efclschool-llvm-18.1.6" + PULP_RISCV_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/efclschool-llvm-18.1.6" before_script: - pwd From 2e2b98a25027f2c6b6955a5cd83869dcfc4908c8 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 25 Oct 2024 10:26:08 +0200 Subject: [PATCH 27/27] Add tiny entry in README + small fix to make checkout-synthesis rule --- Makefile | 2 +- README.md | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b86021c9..10b6dbd7 100644 --- a/Makefile +++ b/Makefile @@ -36,7 +36,7 @@ checkout: $(PULPISSIMO_UTILS)/bender $(PULPISSIMO_UTILS)/bender checkout .PHONY: checkout-synthesis -checkout-synthesis: +checkout-synthesis: $(PULPISSIMO_UTILS)/bender git clone --recursive git@iis-git.ee.ethz.ch:pulp-restricted/pulpissimo-synthesis target/synthesis $(PULPISSIMO_UTILS)/bender update diff --git a/README.md b/README.md index 09ac3018..2ddb1d81 100644 --- a/README.md +++ b/README.md @@ -246,6 +246,13 @@ If you encounter this bug use the following temporary workaround instead to buil VP_WORKAROUND_NONNULL_BUG=yes make build-pulp-sdk ``` +### Non-free synthesis setup +If you have access to the non-free synthesis setup, you can download requirements +with the command +```bash +make checkout-synthesis +``` + ### Building the RTL simulation platform Note you need Questasim or Xcelium to do an RTL simulation of PULPissimo (verilator support planned, but not finished). Intel Modelsim for Intel FPGAs