From c2192f2c4bc60e5276686e3ce85022b4fc39fc4c Mon Sep 17 00:00:00 2001
From: Qi Xuesong <1411979083@qq.com>
Date: Mon, 24 Nov 2025 18:33:42 +0800
Subject: [PATCH] [hardware] add vmv.xs and vfmv.fs in in_lane_op

If a vsetvl instruction that changes SEW is placed immediately before vmv.xs,
the vmv.xs instruction does not trigger a reshuffle because it is not in the
in_lane_op category. This lack of reshuffle leads to vmv.xs writing back an
incorrect value.
---
 hardware/src/ara_dispatcher.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index ec0860505..f1ebd74e9 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -3606,7 +3606,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
         // Is the instruction an in-lane one and could it be subject to reshuffling?
         in_lane_op = ara_req.op inside {[VADD:VMERGE]} || ara_req.op inside {[VREDSUM:VMSBC]} ||
-                     ara_req.op inside {[VMANDNOT:VMXNOR]} || ara_req.op inside {VSLIDEUP, VSLIDEDOWN};
+                     ara_req.op inside {[VMANDNOT:VMXNOR]} || ara_req.op inside {[VMVXS:VSLIDEDOWN]};
         // Annotate which registers need a reshuffle -> |vs1|vs2|vd|
         // Optimization: reshuffle vs1 and vs2 only if the operation is strictly in-lane
         // Optimization: reshuffle vd only if we are not overwriting the whole vector register!