Update open pin and phase check for Cosmo

[ericaasen]

It seems like the RAA229620 has not been added to rendmp for cosmo based on this error message:

λ humility rendmp --open-pin --device 0x75
humility: attached via ST-Link V3
humility rendmp failed: no RAA229618 or ISL68224 with address 117; use `humility pmbus -l` to list devices

Also, when I try to run it on the ISL68224 on cosmo at address 0x5c it times out

λ humility rendmp --open-pin --device 0x5c
humility: attached via ST-Link V3
humility rendmp failed: operation timed out

[nathanaelhuffman]

@bcantrill @mkeeter Note that lacking this functionality prevents us from getting better diagnostics to benchmark other than "check controller and phases" (see https://github.com/oxidecomputer/mfg-troubleshooting/issues/164 as an example). Using this on gimlet has let the techs immediately isolate the problematic phase, so we'd like to support this in cosmo asap also as we ramp mfg.

[cbiffle]

I've gone through and identified all the places where we'd need to change our algorithms to adapt to the '620A part. Unfortunately, this is all based on undocumented stuff from Renesas, so we'll have to talk to them about how to adapt it. Some of the questions I've been able to infer from the datasheet, but we're going to send the following open questions in email:

Fault Disable Register: on prior parts we wrote a register via DMA to disable
all input and output faults. (On the '618 this register was at 0xE932). Is there
a corresponding register on the '620A, and if so, what is its address for DMA
and are there any behavioral distinctions we should be aware of?

EA5B: we currently read the contents of EA5B and then write it back with its low
bit cleared on the '618. Is this behavior appropriate for the '620A? Also, what
should we call this register in our documentation?

Phase Enable Register: we access the Phase Enable Register at 0xE9C2 on all
prior parts. Has this changed on the '620A?

Open-Pin and Mask registers: on the '618 we read registers at 0xBE/0xBF for
open-pin state and 0xE904/E905 for the corresponding masks. Are these locations
still valid on the '620A? Is the layout of bits in the registers the same? In
particular, on the '618 we process 20 phases in the low-order bits followed by
VSEN0/VSEN1 in the higher-order bits -- are VSEN0/VSEN1 at the same bit
offsets on the '620A, or do they immediately follow its 12 phases?