cleanup peripheral register addressing code

There is no need to duplicate the "<= DR_REG_MAG_DIRECT" check
in two functions. Now the _soc_reg_to_ulp_periph_sel() function
is used only for "full addresses" (as it was some commits ago)
and will return a ValueError if used with direct ULP addresses.

This commit also masks values correctly when setting the addr
and periph_sel fields for "direct ULP addresses", so only the
bits we're interested in actually get used (rather than being
implicitly trimmed because there aren't more bits available in
a field).

Author: wnienhaus

esp32_ulp/opcodes.py

@@ -358,9 +358,7 @@ def get_cond(arg):
 
 def _soc_reg_to_ulp_periph_sel(reg):
     # Map SoC peripheral register to periph_sel field of RD_REG and WR_REG instructions.
-    if reg <= DR_REG_MAX_DIRECT:
-        ret = RD_REG_PERIPH_RTC_CNTL
-    elif reg < DR_REG_RTCCNTL_BASE:
+    if reg < DR_REG_RTCCNTL_BASE:
         raise ValueError("invalid register base")
     elif reg < DR_REG_RTCIO_BASE:
         ret = RD_REG_PERIPH_RTC_CNTL
@@ -378,8 +376,8 @@ def _soc_reg_to_ulp_periph_sel(reg):
 def i_reg_wr(reg, high_bit, low_bit, val):
     reg = get_imm(reg)
     if reg <= DR_REG_MAX_DIRECT:  # see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
-        _wr_reg.addr = reg
-        _wr_reg.periph_sel = reg >> 8
+        _wr_reg.addr = reg & 0xff
+        _wr_reg.periph_sel = (reg & 0x300) >> 8
     else:
         _wr_reg.addr = (reg & 0xff) >> 2
         _wr_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)
@@ -393,8 +391,8 @@ def i_reg_wr(reg, high_bit, low_bit, val):
 def i_reg_rd(reg, high_bit, low_bit):
     reg = get_imm(reg)
     if reg <= DR_REG_MAX_DIRECT:  # see https://github.com/espressif/binutils-esp32ulp/blob/master/gas/config/tc-esp32ulp_esp32.c
-        _rd_reg.addr = reg
-        _rd_reg.periph_sel = reg >> 8
+        _rd_reg.addr = reg & 0xff
+        _rd_reg.periph_sel = (reg & 0x300) >> 8
     else:
         _rd_reg.addr = (reg & 0xff) >> 2
         _rd_reg.periph_sel = _soc_reg_to_ulp_periph_sel(reg)